A semiconductor integrated circuit (IC) is generally susceptible to an electrostatic discharge (ESD) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. Therefore, an ESD protection is necessary for all the integrated circuits and different approaches must be taken in different applications.
In a system with a positive power supply (VDD), a relative ground or lower voltage (VSS), and one or more input pins, an ESD may occur at one of the input pins in four different modes: positive-to-VSS(PS) mode, negative-to-VSS(NS) mode, positive-to-VDD(PD) mode, and negative-to-VDD(ND) mode. Each of the modes is defined as follows:
PS mode: ESD at an input pin with positive polarity with respect to the VSS pin when the VDD pin and the other input/output pins are floating;
NS mode: ESD at an input pin with negative polarity with respect to the VSS pin when the VDD pin and the other input/output pins are floating;
PD mode: ESD at an input pin with positive polarity with respect to the VDD pin when the VSS pin and the other input/output pins are floating; and
ND mode: ESD at an input pin with negative polarity with respect to the VDD pin when the VSS pin and the other input/output pins are floating.
In a complete system such as a computer, there are generally more than one power supply voltage. Different sub-systems use different supply voltages. Communications between such different sub-systems requires a mixed-voltage input/output (I/O) buffer circuit to transfer signals with different voltage levels, and ESD protection for such a mixed-voltage I/O buffer circuit is also necessary.
Stacked NMOS transistors, in which a diffusion region in the substrate constructs a source region of one transistor and a drain region of another, are often used in an ESD protection circuit. The diffusion region shared by the transistors renders the stacked NMOS transistors advantageous over a conventional cascade configuration of two NMOS transistors because stacked NMOS transistors have a controllable triggering voltage and a holding voltage for both transistors tailored by altering the length of the shared diffusion area. The stacked NMOS transistors are also able to avoid problems often associated with a single NMOS transistor such as hot carrier degradation and time dependent dielectric breakdown.
An example of incorporating stacked NMOS transistors in ESD protection circuits is shown in FIG. 1. An I/O pad 102 is coupled to an ESD protection circuit 110 and a driver circuit 120. Stacked NMOS transistors 112 and 122 are used in ESD protection circuit 110 and driver circuit 120, respectively. Stacked NMOS transistors 112 comprise an NMOS transistor 114 with its gate (not numbered) coupled to the power supply VDD, and an NMOS transistor 116 with its gate (not numbered) and source (not numbered) coupled to ground, or VSS. Stacked NMOS transistors 122 include an NMOS transistor 124 with its gate (not numbered) coupled to the power supply VDD and an NMOS transistor 126 to receive a driving signal from a previous stage (not shown).
Under normal operation conditions, ESD protection circuit 110 is off because the gate of NMOS transistor 116 has a bias lower than its threshold voltage. When an ESD appears on I/O pad 102, a mechanism called snapback takes place in stacked NMOS transistors 112 and conducts the ESD current to ground, or VSS, through a substrate current in NMOS transistors 114 and 116 that turns on a parasitic lateral bipolar junction transistor (LBJT) (not shown) of stacked NMOS transistors 112. The snapback phenomenon is well-known to one skilled in the art and thus will not be described in detail.
Although stacked NMOS transistors have advantages over a single NMOS transistor, they generally have a higher trigger voltage, higher snapback breakdown voltage, and lower secondary breakdown current due to a wider base width of the LBJT as compared to that of the single NMOS transistor.